Speciication and Veriication of Polling Real-time Systems

Formal methods for real-time systems are an important topic of contemporary research. The aim is to cope with the additional complexity of \time" in speciication and veriication. In Die99a] we present an approach to the correct design of real-time programs implemented on \Programmable Logic Controllers" (PLCs). This hardware executes repeatedly an application program whereas each cycle has an upper time bound. The central device in our approach is the notion of \PLC-Automaton" which provides an abstract view on PLC programs. For PLC-Automata the following results are presented in Die99a]: 1. It is possible to generate PLC source code from a PLC-Automaton. Also constraints on both the speed of the PLC and on the accuracy of time measurement are derived. 2. A logical semantics in terms of Duration Calculus is developed. Since this semantics considers the cyclic behaviour, computation speed, and timer tolerances a realistic model of the real-world behaviour is given. 3. Several ways to compose PLC-Automata are deened and described semantically. 4. An alternative operational semantics in terms of Timed Automata is given. It is provably consistent with the Duration Calculus semantics. Hence, model-checking PLC-Automata is possible due to this semantics. Moreover, we examine techniques for building abstractions of these Timed Automata models. 5. A formal synthesis procedure for \Implementables", a sublanguage of Duration Calculus, is derived that produces a PLC-Automaton implementing the Implementables-speciication if and only if there exists an implementing PLC-Automaton.